The present invention relates generally to phase startable clock devices and more particularly to a phase startable clock device for a digitizing instrument having deterministic phase error correction for improved jitter performance.
In a high speed digitizing instrument, an analog input signal is sampled and quantized during an acquisition interval under control of a sampling strobe signal. The sampling strobe signal may be, or may be derived from, a high frequency sinusoidal signal. It may be desired that the high frequency sinusoidal signal start with a known phase at a fixed time following a control signal transition that is representative of a trigger event. It is known to generate such a high frequency sinusoidal signal using a circuit known as a phase startable clock.
U.S. Pat. No. 5,402,019 describes a phase startable clock device having improved jitter performance and minimal start-up time delay. The phase startable clock device has a stable oscillator generating a sinusoidal signal that is applied to a phase splitter. The phase splitter outputs sinusoidal signals are in quadrature phase or 90xc2x0 apart and have gains A and B. Matching of the gains A and B and having an exact quadrature relationship between the sinusoidal signals are not critical for operation of the device. Each phase shifted sinusoidal signal is coupled to a respective multiplier and track-and-hold circuit. A control transition signal from a control signal source in the form of a trigger signal is applied to each track-and-hold. The held phase values on the respective track-and-hold circuits are cross-coupled to the multipliers. The outputs of the multipliers are summed in a summing circuit to generate an output signal with a predetermined startup phase relative to the trigger transition.
In operation, the phase startable clock device generates a constant value at the output from the summing circuit when the track-and-hold circuits are tracking the phase shifted sinusoidal signals. When a trigger transition occurs, the track-and-hold circuits hold the phase values of the phase shifted sinusoidal signal. The phase values are applied to the multipliers which generate weighted sinusoidal signals based on the held phase values. The weighted sinusoidal signals are added together in the summing circuit to produce the output signal. The output of the phase startable clock device is used as a coarse time delay for a strobe generator. The strobe generator has a digital counter that is loaded with a coarse delay value from a controller. The output of the phase startable clock device is applied to the counter which increments or decrements the counter. The counter increments to a terminal count or decrements to zero whereupon a strobe pulse is generated and applied to an analog time interpolator circuit. The controller provides a digital threshold value to a digital-to-analog converter which converts the digital value to an analog threshold value which is applied to the interpolator circuit. The strobe signal from the counter initiates the generation of a ramp signal in the interpolator circuit. The interpolator circuit generates an output strobe pulse to a sampler circuit when the ramp signal equals the analog threshold value.
The almost instantaneous phase shift or synchronization of the sinusoidal signal phase to the external triggering event is not perfect due to nonlinear effects in the analog processing circuits in the phase startable clock device. The non-ideal circuit operation translates into systematic trigger to gated clock or strobe timing delay errors. What is needed is a phase startable clock device for a sampling time base in a digitizing instrument that reduces the residual time error or deterministic jitter error to more accurately acquire samples of an input signal.
Accordingly, the present invention is directed to a phase startable clock device and digitizing instrument having deterministic phase error correction. The phase startable clock device has a phase gate receiving phase shifted continuous sinusoidal signals. The sinusoidal signals are applied to respective track-and-hold circuits and multipliers. The track-and-hold circuits receive a trigger signal that captures and holds the phase values of the sinusoidal signal. The phase values are applied to phase correction circuitry and infinite track-and-hold circuitry. The phase correction circuitry has A/D converters that convert the analog phase values to digital phase values. The digital phase values are coupled to a phase pointer calculator that generates a phase pointer value derived from the digital phase values. The phase pointer indexes into phase lookup tables equaling in number the number of phase shifted continuous sinusoidal signals. The phase lookup tables output phase correction values that are applied to D/A converters. The digital-to-analog analog converters generate analog voltages representative of the phase correction values. The analog phase correction values are coupled to respective summing circuits with each circuit receiving the phase values held on the track-and-hold circuits. The summation circuits combine the respective phase correction values and the phase values and apply the resulting values to the inputs of the multiplier circuits. The multiplier circuits generate outputs that are summed together in a signal summation circuit to generate and output signal with a predetermined startup phase relative to the control input signal transition.
The optional infinite track-and-hold circuit includes A/D converters that receive the phase values held on the track-and-hold circuits. The A/D converters generate digital phase values that are coupled to a phase pointer calculation. The phase pointer calculator generates a phase pointer value that is used to index into phase lookup tables equaling in number the number of phase shifted continuous sinusoidal signals. The phase lookup tables output phase lookup correction values that are applied to a summation circuit that also receives the digital phase values. The summation circuit combines the respective digital phase values with the digital phase lookup correction values. The respective summed outputs of the summation circuit are coupled to D/A converters. The D/A converters generate analog voltage representative of corrected replica phase values of the phase values held on the track-and-hold circuits. The corrected replica phase values are applied to second input ports of respective multiplexers that receive the corrected phase value at their first input ports. The multiplexers selectively couple the corrected phase values to the multipliers during a first time period and the corrected replica phase values during a second time period.
The output of the phase startable clock device is a clock signal that is applied to a strobe generator. The strobe generator includes counter circuitry and interpolator circuitry. The strobe generator receives strobe delay input that loads the counter circuitry with a coarse delay value and the interpolator with a fine delay value. The clock from the phase startable clock device increments or decrements the counter until a terminal or zero count is reached whereupon a ramp strobe pulse is generated. The ramp strobe pulse initiates the generation of a ramp signal that is applied to the interpolator. The ramp continues until it reaches a threshold value defined by the fine delay value whereupon a sampling strobe is generated. The sampling strobe is used to strobe an input sampler that receives an input signal under test. The sampler acquires waveform samples of the signal under test. The waveform samples are stored in memory in time locations for later retrieval and processing.
In the preferred embodiment of the present invention, the phase startable clock device has a three phase gate. The three phase gate receives three phase shifted sinusoidal input signal at 0xc2x0, 120xc2x0 and 240xc2x0. The phase gate circuitry is then provided with three track-and-hold circuits, three summation circuits and three multiplier circuits. The phase correction circuitry and the infinite track-and-hold circuitry also has three A/D converters, three phase lookup table and thee D/A converters.
A further alternative to the phase startable clock device is the replacement of the phase lookup correction table with a time-error versus phase lookup table. The time-error versus phase lookup table is used to reorder the acquired waveform samples in time after acquisition to remove the deterministic phase error existing in the clock device. For this to happen, the digitized phase values from the infinite track-and-hold circuit are associated with each sample in the recorded waveform. The time-error versus phase lookup table is used during the first time period of the phase startable clock device and the infinite track-and-hold is used during the second period of time.
The objects, advantages and novel features of the present invention are apparent from the following detailed description when read in conjunction with the appended claims and attached drawings.